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Covering silicon wafers, cells, and modules—every step is engineered for efficiency.
Covering silicon wafers, cells, and modules—every step is engineered for efficiency.
|
N-Type |
Wafer Model |
Thickness Tolerance / μm |
TTV / μm |
Saw Mark / μm |
Resistivity |
Minority Carrier Lifetime / μs |
Oxygen Content / ppma |
Carbon Content / ppma |
|
N |
182.2 × 183.75 |
130 ± 8 |
≤ 20 |
≤ 12.5 |
0.6–1.6 |
≥ 1000 |
≤ 11 |
≤ 1 |
|
N |
182.2 × 182.2 |
130 ± 8 |
≤ 20 |
≤ 12.5 |
0.6–1.6 |
≥ 1000 |
≤ 11 |
≤ 1 |
|
N |
182.3 × 210 |
130 ± 8 |
≤ 20 |
≤ 12.5 |
0.6–1.6 |
≥ 1000 |
≤ 11 |
≤ 1 |
|
N |
210 × 210 |
130 ± 8 |
≤ 20 |
≤ 12.5 |
0.6–1.6 |
≥ 1000 |
≤ 11 |
≤ 1 |
|
N |
210 × 105 |
110 +15 / -10 |
≤ 25 |
≤ 12.5 |
0.3–2.1 |
≥ 1000 |
≤ 14 |
≤ 1 |
|
N |
182.3 × 105 |
130 ± 10 |
≤ 25 |
≤ 12.5 |
0.4–1.6 |
≥ 4000 |
≤ 13 |
≤ 1 |
|
Note: Electrical performance and appearance parameters of silicon wafers can be customized according to customer requirements. |
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